Dr. Bheemappa Halavar
Assistant Professor
Academic Qualifications
Education:
PhD, 2020
National Institute of Technology Karnataka Surathkal
Thesis Title: Design of power and performance optimal 3D-NoC architectures.
Research Areas of Interest
Research Areas:
Network on chips(NoC)-System Architecture, High-Performance Computing and Named data networking.
Awards / Honours
Projects
Publications
2020
- Power and Performance Analysis of 3D Network-on-Chip Architectures, Bheemappa Halavar and Basavaraj Talawar, Computers & Electrical Engineering Volume 83, May 2020, 106592.
2019
- Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3DNoC architectures, Bheemappa Halavar, Ujjwal Pasupulety and Basavaraj Talawar, Simulation Modelling Practice and Theory Volume 96, November 2019, 101929.
2018
- "Floorplan based performance evaluation of 3d variants of mesh and BFT networks-on-chip.", Bheemappa Halavar and Basavaraj Talawar, 2018 International Conference on Signal Processing and Communications (SPCOM). IEEE, 2018.
- "Accurate performance analysis of 3d mesh network on chip architectures.", Bheemappa Halavar and Basavaraj Talawar, 2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT). IEEE, 2018.
- "OP3DBFT: A power and performance optimal 3D BFT NoC architecture." International Conference on Intelligent Systems Design and Applications. Springer, 2018.
- "Accurate Power and Latency Analysis of a Through-Silicon Via (TSV).",Pasupulety, Ujjwal, Bheemappa Halavar, and Basavaraj Talawar. 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI). IEEE, 2018.
- "Thermal Aware Design for Through-Silicon Via (TSV) based 3D Network-on-Chip (NoC) Architectures.", Pasupulety, Ujjwal, Bheemappa Halavar, and Basavaraj Talawar, International Symposium on Embedded Computing and System Design (ISED). IEEE, 2018.
